The present invention relates to integrated circuit memory devices and, more particularly, to integrated circuit first-in first-out (FIFO) memory devices.
Semiconductor memory devices can typically be classified on the basis of memory functionality, data access patterns and the nature of the data storage mechanism. For example, distinctions are typically made between read-only memory (ROM) devices and read-write memory (RWM) devices. The RWM devices typically have the advantage of offering both read and write functionality with comparable data access times. Typically, in RWM devices, data is stored either in flip-flops for xe2x80x9cstaticxe2x80x9d memory devices or as preset levels of charge on a capacitor in xe2x80x9cdynamicxe2x80x9d memory devices. As will be understood by those skilled in the art, static memory devices retain their data as long as a supply of power is maintained, however, dynamic memory devices require periodic data refreshing to compensate for potential charge leakage. Because RWM devices use active circuitry to store data, they belong to a class of memory devices known as xe2x80x9cvolatilexe2x80x9d memory devices because data stored therein will be lost upon termination of the power supply. ROM devices, on the other hand, may encode data into circuit topology (e.g., by blowing fuses, removing diodes, etc.). Because this latter type of data storage may be hardwired, the data cannot be modified, but can only be read. ROM devices also typically belong to a class of memory devices known as xe2x80x9cnonvolatilexe2x80x9d memory devices because data stored therein will typically not be lost upon termination of the power supply. Other types of memory devices that have been more recently developed are typically referred to as nonvolatile read-write (NVRWM) memory devices. These types of memory devices include EPROM (erasable programmable read-only memory), E2PROM (electrically erasable programmable read-only memory), and flash memories, for example.
An additional memory classification is typically based on the order in which data can be accessed. Here, most memory devices belong to the random-access class, which means that memory locations can be read from or written to in random order. Notwithstanding the fact that most memory devices provide random-access, typically only random-access RWM memories use the acronym RAM. Alternatively, memory devices may restrict the order of data access to achieve shorter data access times, reduce layout area and/or provide specialized functionality. Examples of such specialized memory devices include buffer memory devices such as first-in first-out (FIFO) memory devices, last-in first-out (LIFO or xe2x80x9cstackxe2x80x9d) memory devices, shift registers and content-addressable memory (CAM) devices.
A final classification of semiconductor memories is based on the number of data input and data output ports associated with the memory cells therein. For example, although most memory devices have unit cells therein that provide only a single port, which is shared to provide an input and output path for transfer of data, memory devices with higher bandwidth requirements often have cells therein with multiple input and output ports. However, the addition of ports to unit memory cells typically increases the complexity and layout area requirements for these higher bandwidth memory devices.
Single-port memory devices are typically made using static RAM cells if fast data access times are a requirement, and dynamic RAM cells if low cost is a primary requirement. Many FIFO memory devices use dual-port RAM based designs with self-incrementing internal read and write pointers to achieve fast fall-through capability. As will be understood by those skilled in the art, fall-through capability is typically measured as the time elapsing between the end of a write cycle into a previously empty FIFO and the time an operation to read that data may begin. Exemplary FIFO memory devices are more fully described and illustrated at section 2.2.7 of a textbook by A. K. Sharma entitled xe2x80x9cSemiconductor Memories: Technology, Testing and Reliabilityxe2x80x9d, IEEE Press (1997).
In particular, dual-port SRAM-based FIFOs typically utilize separate read and write pointers to advantageously allow read and write operations to occur independently of each other and achieve fast fall-through capability as data written into a dual-port SRAM FIFO can be immediately accessed for reading. Since these read and write operations may occur independently, independent read and write clocks having different frequencies may be provided to enable the FIFO to act as a buffer between peripheral devices operating at different rates. Unfortunately, a major disadvantage of typical dual-port SRAM-based FIFOs is the relatively large unit cell size for each dual-port SRAM cell therein. Thus, for a given semiconductor chip size, dual-port buffer memory devices typically provide less memory capacity relative to single-port buffer memory devices. For example, using a standard DRAM cell as a reference unit cell consuming one (1) unit of area, a single-port SRAM unit cell typically may consume four (4) units of area and a dual-port SRAM unit cell typically may consume sixteen (16) units of area. Moreover, the relatively large unit cells of a dual-port SRAM FIFO limit the degree to which the number of write operations can exceed the number of read operations, that is, limit the capacity of the FIFO.
To address these limitations of dual-port buffer memory devices, single-port buffer memory devices have been developed to, among other things, achieve higher data capacities for a given semiconductor chip size. For example, U.S. Pat. No. 5,546,347 to Ko et al. entitled xe2x80x9cInterleaving Architecture And Method For A High Density FIFOxe2x80x9d, assigned to the present assignee, discloses a memory device that has high capacity and uses relatively small single-port memory cells. However, the use of only single port memory cells typically precludes simultaneous read and write access to data in the same memory cell, which means that single-port buffer memory devices typically have slower fall-through time than comparable dual-port memory devices. Moreover, single-port buffer memory devices may use complicated arbitration hardware to control sequencing and queuing of reading and writing operations.
U.S. Pat. No. 5,371,708 to Kobayashi also discloses a FIFO memory device containing a single-port memory array, a read data register for holding read data from the memory array and a write data register for holding write data to the memory array. A bypass switch is also provided for transferring data from the write data register to the read data register so that the memory array can be bypassed during testing of the FIFO to detect the presence of defects therein. However, like the above-described single-port buffer memory devices, simultaneous read and write access to data is not feasible.
Commonly assigned U.S. Pat. Nos. 5,978,307, 5,982,700 and 5,998,478 disclose FIFO memory devices having generally fast fall-through capability. These memory buffers contain a tri-port memory array of moderate capacity having nonlinear columns of tri-port cells therein, which collectively form four separate registers, and a substantially larger capacity supplemental memory array (e.g., DRAM array) having cells therein with reduced unit cell size. The tri-port memory array has a read port, a write port and a bidirectional input/output port. The tri-port memory array communicates internally with the supplemental memory array via the bidirectional input/output port and communicates with external devices (e.g., peripheral devices) via the read and write data ports. Efficient steering circuitry is also provided by a bidirectional crosspoint switch that electrically couples terminals (lines IO and IOB) of the bidirectional input/output port in parallel to bit lines (BL and BLB) in the supplemental memory array during a write-to-memory time interval and vice versa during a read-from-memory time interval.
Notwithstanding the above described FIFO memory devices, there still exists a need to develop higher speed FIFO memory devices having expanded functionality and increased data capacity. The also exists a need for FIFO memory devices that provide faster data transfer for such applications as network, video, telecommunications and data communications.
First-in first-out (FIFO) memory devices according to first embodiments of the present invention include a plurality of memory devices that are configured to support any combination of dual data rate (DDR) or single data rate (SDR) write modes that operate in-sync with a write clock signal (WCLK) and DDR or SDR read modes that operate in-sync with a read clock signal (RCLK). These FIFO memory devices also provide flexible x4N, x2N and xN bus matching on both read and write ports and enable data to be written and read on both rising and falling edges of the write and read clock signals. These FIFO memory devices represent a significant alternative to increasing data rate without extending the width of input or output busses or the internal speed of the devices. They are also effective in applications that require buffering large amounts of data and matching busses of unequal sizes. Custom flag generation and retransmit circuitry is also provided that can efficiently handle any combination of DDR and SDR read and write modes.
These FIFO memory devices may include write control circuitry that provides the plurality of memory devices with write data in-sync with rising and falling edges of the write clock signal when the FIFO memory device is disposed in the DDR write mode. Likewise, read control circuitry may be included that receives read data from the plurality of memory devices in-sync with rising and falling edges of the read clock signal when the FIFO memory device is disposed in the DDR read mode. The write control circuitry may also be configured to provide the plurality of memory devices with write data in-sync with leading edges of the write clock signal when the FIFO memory device is disposed in a single data rate (SDR) write mode. The read control circuitry may be configured to receive read data from the plurality of memory devices in-sync with leading edges of the read clock signal when the FIFO memory device is disposed in a single data rate (SDR) read mode.
According to one aspect of these first embodiments, the plurality of memory devices may include first and second memory devices that, during the DDR write mode, receive write data in an alternating back-and-forth sequence on alternating rising and falling edges of the write clock signal. These first and second memory devices may also provide read data in an alternating back-and-forth sequence during the DDR read mode. According to another aspect of these first embodiments, the plurality of memory devices include first, second, third and fourth memory devices configured in a preferred quad arrangement. Moreover, when operating in a DDR write mode that supports a x4N write data width, where N is a positive integer, the write control circuitry provides each of the memory devices in the quad arrangement with 4N bits of write data in a sequence that is synchronized with leading and trailing edges of two (2) consecutive cycles of the write clock signal. Alternatively, when operating in a DDR write mode that supports a x2N write data width, the write control circuitry provides each of the memory devices in the quad arrangement with 4N bits of write data in a sequence that is synchronized with trailing edges of four (4) consecutive cycles of the write clock signal. Finally, when operating in a DDR write mode that supports a xN write data width, the write control circuitry provides each of the memory devices in the quad arrangement with 4N bits of write data in a sequence that is synchronized with trailing edges of every other one of eight (8) consecutive cycles of the write clock signal.
According to still further aspects of these first embodiments, when operating in an SDR write mode and supporting the x4N write data width, the write control circuitry provides each of the memory devices in the quad arrangement with 4N bits of write data in a sequence that is synchronized with leading edges of four (4) consecutive cycles of the write clock signal. When operating in an SDR write mode and supporting the x2N write data width, the write control circuitry provides each of the memory devices in the quad arrangement with 4N bits of write data in a sequence that is synchronized with leading edges of every other one of eight (8) consecutive cycles of the write clock signal. Finally, when operating in an SDR write mode and supporting the xN write data width, the write control circuitry provides each of the memory devices in the quad arrangement with 4N bits of write data in a sequence that is synchronized with leading edges of every fourth one of sixteen (16) consecutive cycles of the write clock signal. Analogous operations are also performed when the FIFO memory devices are operating in any combination of DDR and SDR read modes.
First-in first-out (FIFO) memory devices according to second embodiments of the present invention include a plurality of memory devices and an input multiplexer that provides the plurality of memory devices with write data in-sync with rising and falling edges of a write clock signal when the FIFO memory device is disposed in a dual data rate (DDR) write mode. The FIFO memory devices may also include an output multiplexer that receives read data from the plurality of memory devices in-sync with rising and falling edges of a read clock signal when the FIFO memory device is disposed in a DDR read mode. The input multiplexer may comprise an input data buffer and a master latch electrically coupled to an output of the input data buffer. A first bus matching circuit may also be provided that supports any combination of x4N, x2N and xN write modes. This first bus matching circuit is electrically coupled to an output of the master latch. A slave latch is also provided. This slave latch has inputs that are electrically coupled to corresponding outputs of the first bus matching circuit. The outputs of the slave latch are electrically coupled to the plurality of memory devices.
The output multiplexer may also include a second bus matching circuit having inputs that are electrically coupled to receive read data from the plurality of memory devices. First and second output registers may also be provided having inputs that are electrically coupled to first and second output ports of the second bus matching circuit. According to a preferred aspect of these second embodiments, the output multiplexer includes a redirect multiplexer having first and second inputs that are electrically coupled to the first and second output ports and an output electrically coupled to an input of the first output register. This redirect multiplexer is preferably responsive to a single date rate select signal. This single data rate select signal enables the second output register to be bypassed when the FIFO memory device is disposed in a single data rate (SDR) read mode of operation.
First-in first-out (FIFO) memory devices according to third embodiments of the present invention may include a plurality of multi-port cache memory devices that are configured to support any combination of dual data rate (DDR) or single data rate (SDR) write modes and DDR or SDR read modes. These multi-port cache memory devices may include first and second quad-port cache memory devices. Each of these quad-port cache memory devices may include a data input register, a multiplexer and an output register. The data input register may have an input electrically coupled to a first port of the quad-port cache memory device and an output electrically coupled to a second port of the quad-port cache memory device. The multiplexer is responsive to at least one select signal and has a first input electrically coupled to the output of the data input register and a second input electrically coupled to a third port of the quad-port cache memory device. The output register has an input electrically coupled to an output of the multiplexer and an output electrically coupled to a fourth port of the quad-port cache memory device.
First-in first-out (FIFO) memory devices according to fourth embodiments of the present invention may include a plurality of memory devices that are configured to support a dual data rate (DDR) read mode that operates in-sync with leading and trailing edges of a read clock signal and read control circuitry that can handle retransmit operations. This read control circuitry may mark data read from the FIFO memory device in response to a trailing edge of a first cycle of the read clock signal during the DDR read mode. This marking operation may be responsive to an active mark signal. The read control circuitry may also perform retransmit operations that are responsive to an active retransmit signal. These retransmit operations may include retransmitting data in pairs by commencing the retransmission with data previously read from the FIFO memory device in response to a leading edge of the first cycle of the read clock signal before following with the marked read data that was originally read on the trailing edge of the first cycle of the read clock signal.
The embodiments of the present invention also preferably include flag circuitry that can address empty, almost empty, full and almost full conditions within a FIFO memory device having DDR read and write modes. This flag circuitry preferably evaluates an empty (or almost empty) condition in the FIFO memory device by comparing a write counter value that is generated off a trailing edge of the write clock signal against a read counter value that is generated off a leading edge of the read clock signal when the FIFO memory device is disposed in the DDR write mode. This flag circuitry may also evaluate a full (or almost full) condition in the FIFO memory device by comparing a read counter value that is generated off a trailing edge of the read clock signal against a write counter value that is generated off a leading edge of the write clock signal when the FIFO memory device is disposed in the DDR read mode. Other FIFO memory device embodiments may also be provided that include more than two (2) or four (4) memory devices that operate in tandem to provide any combination of DDR and SDR modes.